<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bcm63xx/u-boot/include/cache.h, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/'/>
<updated>2019-05-05T12:48:50Z</updated>
<entry>
<title>dm: cache: Create a uclass for cache</title>
<updated>2019-05-05T12:48:50Z</updated>
<author>
<name>Dinh Nguyen</name>
</author>
<published>2019-04-23T21:55:03Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=84b124db3584d8b3f1a42c1506983323bce9983f'/>
<id>urn:sha1:84b124db3584d8b3f1a42c1506983323bce9983f</id>
<content type='text'>
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</content>
</entry>
</feed>
