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<title>bcm63xx/u-boot/include/altera.h, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/'/>
<updated>2018-12-20T16:12:25Z</updated>
<entry>
<title>arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table</title>
<updated>2018-12-20T16:12:25Z</updated>
<author>
<name>Ang, Chee Hong</name>
</author>
<published>2018-12-20T02:35:15Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=877ec6ebbd247d54706e8f18a5d0c85da229a163'/>
<id>urn:sha1:877ec6ebbd247d54706e8f18a5d0c85da229a163</id>
<content type='text'>
Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.

Signed-off-by: Ang, Chee Hong &lt;chee.hong.ang@intel.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver</title>
<updated>2018-12-20T16:12:25Z</updated>
<author>
<name>Ang, Chee Hong</name>
</author>
<published>2018-12-20T02:35:14Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=c41e660b6bb4405fb511c7af29aad4271f6b39a8'/>
<id>urn:sha1:c41e660b6bb4405fb511c7af29aad4271f6b39a8</id>
<content type='text'>
Enable FPGA reconfiguration support for Stratix 10 SoC.

Signed-off-by: Ang, Chee Hong &lt;chee.hong.ang@intel.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
</author>
<published>2018-05-06T21:58:06Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=83d290c56fab2d38cd1ab4c4cc7099559c1d5046'/>
<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>fpga: altera: Add StratixV support</title>
<updated>2016-03-24T08:47:43Z</updated>
<author>
<name>Stefan Roese</name>
</author>
<published>2016-02-12T12:48:02Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=ff9c4c535a8b722c54d45e77aa083fa08552341d'/>
<id>urn:sha1:ff9c4c535a8b722c54d45e77aa083fa08552341d</id>
<content type='text'>
This patch adds support for programming of the StratixV FPGAs. Programming
is done in this case (board theadorable) via SPI. The board may provide
board specific code for bitstream programming.

This StratixV support will be used by the theadorable board.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: fpga: Add SoCFPGA FPGA programming interface</title>
<updated>2014-10-06T15:46:50Z</updated>
<author>
<name>Pavel Machek</name>
</author>
<published>2014-09-08T12:08:45Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=230fe9b202ff0ca396ad9a564816cc87d42daa6e'/>
<id>urn:sha1:230fe9b202ff0ca396ad9a564816cc87d42daa6e</id>
<content type='text'>
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.

Signed-off-by: Pavel Machek &lt;pavel@denx.de&gt;
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Pavel Machek &lt;pavel@denx.de&gt;

V2: Move the not-CPU specific stuff into drivers/fpga/ and base
    this on the cleaned up altera FPGA support.
</content>
</entry>
<entry>
<title>fpga: altera: Clean up enums in altera.h</title>
<updated>2014-10-06T15:31:42Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2014-09-16T18:48:33Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=d44ef7ffbfef26f71d5811006f00fc82e941fe98'/>
<id>urn:sha1:d44ef7ffbfef26f71d5811006f00fc82e941fe98</id>
<content type='text'>
Get rid of the line-over-80 problems and zap the typedef that
went alongside those enums.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Pavel Machek &lt;pavel@denx.de&gt;
Acked-by: Pavel Machek &lt;pavel@denx.de&gt;
</content>
</entry>
<entry>
<title>whitespace cleanups</title>
<updated>2014-07-22T11:44:27Z</updated>
<author>
<name>Pavel Machek</name>
</author>
<published>2014-07-19T21:50:44Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=3f9eb6e1095b791867975c236bd7ab8b0a51acf4'/>
<id>urn:sha1:3f9eb6e1095b791867975c236bd7ab8b0a51acf4</id>
<content type='text'>
Whitespace cleanups.

Signed-off-by: Pavel Machek &lt;pavel@denx.de&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
</author>
<published>2013-07-08T07:37:19Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=1a4596601fd395f3afb8f82f3f840c5e00bdd57a'/>
<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>fpga: Remove all CONFIG_SYS_* fpga related options</title>
<updated>2013-05-06T08:41:30Z</updated>
<author>
<name>Michal Simek</name>
</author>
<published>2013-05-01T16:05:56Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=b03b25caea1ff3a501161f5bc1ad5e5b5b124e0c'/>
<id>urn:sha1:b03b25caea1ff3a501161f5bc1ad5e5b5b124e0c</id>
<content type='text'>
All these macros are completely unused by any code.
CONFIG_FPGA is not a bitfield anymore.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>fpga: constify to fix build warning</title>
<updated>2011-08-01T13:19:40Z</updated>
<author>
<name>Wolfgang Denk</name>
</author>
<published>2011-07-30T13:33:49Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=e6a857da746d5d7d450e59c0f86664c6b279b1c2'/>
<id>urn:sha1:e6a857da746d5d7d450e59c0f86664c6b279b1c2</id>
<content type='text'>
Fix compiler warning:

cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer type

Adding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.

Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Andre Schwarz &lt;andre.schwarz@matrix-vision.de&gt;
Cc: Murray Jensen &lt;Murray.Jensen@csiro.au&gt;
Acked-by: Andre Schwarz&lt;andre.schwarz@matrix-vision.de&gt;
</content>
</entry>
</feed>
