bcm63xx/u-boot/drivers/timer/Kconfig, branch master

timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver

2019-05-07T03:41:32Z

Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut Cc: Chris Brandt Cc: Nobuhiro Iwamatsu

timer: Add generic driver for RISC-V privileged architecture defined timer

2018-12-18T01:56:26Z

RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel

timer: MediaTek: add timer driver for MediaTek SoCs

2018-11-29T04:04:51Z

This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee Tested-by: Matthias Brugger Reviewed-by: Simon Glass

timer: Sort Kconfig driver entries

2018-11-14T17:16:27Z

This is currently out of order. Sort it. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: tsc: Introduce config option for early timer frequency

2018-10-22T09:51:45Z

So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

Enable CONFIG_TIMER_EARLY with bootstage

2018-10-22T09:51:45Z

In initr_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us(). This call happens before initr_dm(), which inits driver model. On x86 we set gd->timer to NULL in the transition from board_init_f() to board_init_r(). See board_init_f_r() for this assignment. So U-Boot knows there is no timer available in the period immediately after relocation. On x86 the timer_get_us() call is implemented as calls to get_ticks() and get_tbclk(). Both of these call dm_timer_init() to set up the timer, if gd->timer is NULL and the early timer is not available. However dm_timer_init() cannot succeed before initr_dm() is called. So it seems that on x86 if we want to use CONFIG_BOOTSTAGE we must enable CONFIG_TIMER_EARLY. Update the Kconfig to handle this. Note: On most architectures we can rely on the pre-relocation memory still being available, so that gd->timer pointers to a valid timer device and everything works correctly. Admittedly this is not strictly correct since the timer device is set up by pre-relocation U-Boot, but normally this is fine. On x86 the 'CAR' (cache-as-RAM) memory used by pre-relocation U-Boot disappears in board_init_f_r() and any attempt to access it will hang. This is the reason why we must mark the timer as invalid when we get to board_init_f_r(). Signed-off-by: Simon Glass Reviewed-by: Bin Meng

timer: Add MPC83xx timer driver

2018-09-18T06:01:18Z

Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six

timer: dw-apb: Add Designware APB timer driver

2018-08-24T10:05:20Z

Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Ley Foon Tan

timer: Add Cadence TTC timer counter support

2018-05-11T07:23:43Z

This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek

timer: stm32: Add timer support for STM32 SoCs family

2018-03-14T01:45:37Z

This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard