bcm63xx/u-boot/drivers/phy/marvell, branch master

phy: marvell: add SATA comphy RX/TX polarity invert support

2018-09-19T11:54:27Z

This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The 'phy-invert' DT property defines the inverted signals. Signed-off-by: Rabeeh Khoury Signed-off-by: Baruch Siach Signed-off-by: Stefan Roese

phy: marvell: Support changing SERDES map in board file

2018-09-19T06:59:26Z

This adds a weak definition of comphy_update_map to comphy_core, which does nothing. If this function is defined elsewhere, for example in board file, the board file can change some parameters of SERDES configuration. This is needed on Turris Mox, where the SERDES speed on lane 1 has to be set differently when SFP module is connected and when Topaz Switch module is connected. This is a temporary solution. When the comphy driver for armada-3720 will be added to the kernel, the comphy driver in u-boot shall also be updated and this should be done differently then. Signed-off-by: Marek Behun Signed-off-by: Stefan Roese

phy: marvell: a3700: Fix compatible string for ehci

2018-05-14T08:01:56Z

The DTS file for armada-37xx uses the string "marvell,armada3700-ehci", but the code searched for "marvell,armada-3700-ehci". Signed-off-by: Marek Behun Signed-off-by: Stefan Roese

phy: marvell: core: Cosmetic fixes

2018-05-14T08:00:15Z

Move the reg_set* functions into comphy.h as static inline functions. Change return type of get_*_string to const char *. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese

phy: marvell: a3700: Save/restore selector reg in SGMII init

2018-05-14T08:00:15Z

In SGMII initialization PIN_PIPE_SEL has to be zero when resetting the PHY. Since comphy_mux already set the selector register to correct values, we have to store it's value before setting it to 0 and restore it after SGMII init. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese

phy: marvell: a3700: Use comphy_mux on Armada 37xx.

2018-05-14T08:00:15Z

Lane 0 supports SGMII1 and USB3. Lane 1 supports SGMII0 and PEX0. Lane 2 supports SATA0 and USB3. This is needed for Armada 37xx. This introduces new device tree bindings. AFAIK there is currently no driver for Armada 37xx comphy in Linux. When such a driver will be pushed into Linux, this will need to be rewritten accordingly. Signed-off-by: Marek Behun Signed-off-by: Stefan Roese

phy: marvell: a3700: Fix SGMII cfg and stat register addresses

2018-05-14T08:00:15Z

The register addresses on lanes 0 and 1 are switched, first comes 1 and then 0. Signed-off-by: Marek Behun Signed-off-by: Stefan Roese

phy: marvell: mux: Support nontrivial node order in selector register

2018-05-14T08:00:15Z

Currently comphy_mux supports only trivial order of nodes in pin selector register, that is lane N on position N*bitcount. Add support for nontrivial order, with map stored in device tree property mux-lane-order. This is needed for Armada 37xx. As far as I know, there is no driver for Armada 37xx comphy in the kernel. When such a driver comes, this will need to be rewritten to support the device tree bindings from the kernel. Signed-off-by: Marek Behun Signed-off-by: Stefan Roese

phy: marvell: a3700: revise the USB3 comphy setting during power on

2018-05-14T08:00:15Z

This commit is based on commit d9899826 by zachary from u-boot-marvell, see github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/d9899826 - According to design specification, the transmitter should be set to high impedence mode during electrical idle. Thus transmitter should detect RX at high impedence mode also, and delay is needed to accommodate high impedence off latency. Otherwise the USB3 will have detection issue that most of the time the USB3 device can not be detected at all, or be detected as USB2 device sometimes. Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1 Bit 6: set to 1 to let Tx detect Rx at HiZ mode Bit [3:4]: set to 2 to be delayed by 2 clock cycles Bit 0: set to 1 to set transmitter to high impedance mode during idle. - USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2 (emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed to select 0x1(3.5dB emphasize). Thus need to override what comes from the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register 0x181 and bit0 of register 0x180). - According to USB3 application note, need to update below comphy registers: Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1) Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF) Signed-off-by: Marek Behun Signed-off-by: Stefan Roese

phy: marvell: a3700: Set USB3 RX wait depending on ref clock

2018-05-14T08:00:15Z

According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7 when reference clock is at 25 MHz. The specification (at least the version I have) does not mentoin the setting for 40 MHz reference clock, but Marvell's U-Boot sets 0xC in that case. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese