<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bcm63xx/u-boot/drivers/pci, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/'/>
<updated>2019-06-21T14:07:11Z</updated>
<entry>
<title>pci: Avoid assigning PCI resources that are below 0x1000</title>
<updated>2019-06-21T14:07:11Z</updated>
<author>
<name>Bin Meng</name>
</author>
<published>2019-06-05T14:26:44Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=5fafd7e35f03a28748456fe2277f073846946b2f'/>
<id>urn:sha1:5fafd7e35f03a28748456fe2277f073846946b2f</id>
<content type='text'>
commit b7598a43f2b4 ("[PATCH] Avoid assigning PCI resources from
zero address") only moved the bus lower address to 0x1000 if the
given bus start address is zero. The comment said 0x1000 is a
reasonable starting value, hence we'd better apply the same
adjustment when the given bus start address is below 0x1000.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>dm: pci: add Freescale PowerPC PCIe driver</title>
<updated>2019-06-20T05:14:45Z</updated>
<author>
<name>Hou Zhiqiang</name>
</author>
<published>2019-04-24T14:33:02Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=b89e3d9250046c3e7c956fd5e7a14364747433a4'/>
<id>urn:sha1:b89e3d9250046c3e7c956fd5e7a14364747433a4</id>
<content type='text'>
Add PCIe DM driver for Freescale PowerPC PCIe controllers.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: imx: Add DM and DT support</title>
<updated>2019-06-11T08:42:48Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-06-09T01:50:55Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=a11c0f44b77b745519e35d30fc5eecb6206107fb'/>
<id>urn:sha1:a11c0f44b77b745519e35d30fc5eecb6206107fb</id>
<content type='text'>
Add DM support and support for probing the iMX PCI driver from DT.
The legacy non-DM support is retained, however shall be removed once
DM PCI is the only option remaining.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>pci: imx: Pass driver private data around</title>
<updated>2019-06-11T08:42:48Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-06-09T01:50:54Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=d2cc2e86f8e12393f2adf47c9a8694475e92e05a'/>
<id>urn:sha1:d2cc2e86f8e12393f2adf47c9a8694475e92e05a</id>
<content type='text'>
Pass the driver private data around the driver as much as possible, instead
of having it as a static global variable. This is done in preparation for
the DM conversion, no functional change.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>pci: imx: Fix potential 64bit memory access clamping</title>
<updated>2019-06-11T08:42:48Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-06-09T01:50:53Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=90f87fb5258c57bbb8497ac23454e659169483e4'/>
<id>urn:sha1:90f87fb5258c57bbb8497ac23454e659169483e4</id>
<content type='text'>
The driver limits the config space base to 32bit, however it can be
64bit on 64bit iMX hardware too. Remove that limitation. This patch
has no impact on the iMX6, which is the only SoC currently supported
by this driver.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>pci: imx: Factor out hard-coded register base addresses</title>
<updated>2019-06-11T08:42:48Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-06-09T01:50:52Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=33f794be36e846a522c7020e642a1e89c0769b17'/>
<id>urn:sha1:33f794be36e846a522c7020e642a1e89c0769b17</id>
<content type='text'>
Pull out hard-coded register base addresses into driver private
structure in preparation for DM conversion. No functional change.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-sh</title>
<updated>2019-05-27T00:18:20Z</updated>
<author>
<name>Tom Rini</name>
</author>
<published>2019-05-27T00:18:20Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=c18b103657d9541305a45a1fb21f979c317fba49'/>
<id>urn:sha1:c18b103657d9541305a45a1fb21f979c317fba49</id>
<content type='text'>
- Gen3 PCIe driver + enablement on Salvator-X platforms.
- Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon.
- SDHI HS400 fixes ported from latest BSP and datasheet.
</content>
</entry>
<entry>
<title>pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs</title>
<updated>2019-05-22T06:54:24Z</updated>
<author>
<name>Hou Zhiqiang</name>
</author>
<published>2019-04-08T10:15:54Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=1d341bc4b6b357e7348ab4393247e369aeb30aa6'/>
<id>urn:sha1:1d341bc4b6b357e7348ab4393247e369aeb30aa6</id>
<content type='text'>
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller
to update device tree nodes to convey SMMU stream IDs in the
device tree.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs</title>
<updated>2019-05-22T06:54:24Z</updated>
<author>
<name>Hou Zhiqiang</name>
</author>
<published>2019-04-08T10:15:46Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=07ce19f5e9ad637caa8cb2b6db45a6a28d2d69a1'/>
<id>urn:sha1:07ce19f5e9ad637caa8cb2b6db45a6a28d2d69a1</id>
<content type='text'>
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe
controller is based on the Mobiveil IP, which is compatible
with the PCI Express™ Base Specification, Revision 4.0.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Signed-off-by: Bao Xiaowei &lt;Xiaowei.Bao@nxp.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: renesas: Add RCar Gen3 PCIe controller driver</title>
<updated>2019-05-21T20:15:31Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2018-10-16T10:49:19Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=776abedef473659f165dd018388e8b5d81a5c54c'/>
<id>urn:sha1:776abedef473659f165dd018388e8b5d81a5c54c</id>
<content type='text'>
Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs.
The PCIe on Gen3 is used both to connect external PCIe peripherals.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
</feed>
