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<title>bcm63xx/u-boot/drivers/net/designware.c, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
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<updated>2019-01-24T17:35:27Z</updated>
<entry>
<title>net: designware: clear padding bytes</title>
<updated>2019-01-24T17:35:27Z</updated>
<author>
<name>Simon Goldschmidt</name>
</author>
<published>2018-11-17T09:24:42Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=7efb75b11480c46077b44df70aa30d375bf761be'/>
<id>urn:sha1:7efb75b11480c46077b44df70aa30d375bf761be</id>
<content type='text'>
Short frames are padded to the minimum allowed size of 60 bytes.
However, the designware driver sends old data in these padding bytes.
It is common practice to zero out these padding bytes ro prevent
leaking memory contents to other hosts.

Fix the padding code to zero out the padded bytes at the end.

Tested on socfpga gen5.

Signed-off-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>net: designware: fix tx packet length</title>
<updated>2019-01-24T17:35:27Z</updated>
<author>
<name>Simon Goldschmidt</name>
</author>
<published>2018-11-17T09:24:41Z</published>
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<id>urn:sha1:ae8ac8d423675904fdbf1510ad71e37d71db0568</id>
<content type='text'>
The designware driver has a bug in setting the tx length into the dma
descriptor: it always or's the length into the descriptor without
zeroing out the length mask before.

This results in occasional packets being transmitted with a length
greater than they should be (trailer). Due to the nature of Ethernet
allowing such a trailer, most packets seem to be parsed fine by remote
hosts, which is probably why this hasn't been noticed.

Fix this by correctly clearing the size mask before setting the new
length.

Tested on socfpga gen5.

Signed-off-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>net: designware: add meson meson axg compatible</title>
<updated>2018-11-26T13:40:10Z</updated>
<author>
<name>Neil Armstrong</name>
</author>
<published>2018-11-08T16:16:11Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=71a38a8e8e2828a3e1165585e134802be8ee05a7'/>
<id>urn:sha1:71a38a8e8e2828a3e1165585e134802be8ee05a7</id>
<content type='text'>
Add the compatible string for the upcoming Amlogic AXG SoC family.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
</entry>
<entry>
<title>net: designware: add meson meson gxbb compatible</title>
<updated>2018-11-26T13:40:10Z</updated>
<author>
<name>Neil Armstrong</name>
</author>
<published>2018-09-10T14:44:14Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=ec353ad1b6f66832f641f7ab00c3ee9bbf0d31ff'/>
<id>urn:sha1:ec353ad1b6f66832f641f7ab00c3ee9bbf0d31ff</id>
<content type='text'>
Add the compatible string for the Amlogic GXBB SoC family.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
</entry>
<entry>
<title>net: designware: Add reset ctrl to driver</title>
<updated>2018-07-09T19:28:28Z</updated>
<author>
<name>Ley Foon Tan</name>
</author>
<published>2018-06-14T10:45:23Z</published>
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<id>urn:sha1:495c70f9dfad1a5428ec84b52e8667ea4760ecd6</id>
<content type='text'>
Add code to reset all reset signals as in Ethernet DT node. A reset
property is an optional feature, so only print out a warning and do not
fail if a reset property is not present.

If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.

Signed-off-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>net: designware: set the PS bit when resetting DMA bus in MII configuration</title>
<updated>2018-06-13T18:54:17Z</updated>
<author>
<name>Quentin Schulz</name>
</author>
<published>2018-06-04T10:17:33Z</published>
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<id>urn:sha1:c61221948c30710f2316b264f61efbf61c92a4aa</id>
<content type='text'>
On the SPEAr600 SoC, which has the dwmac1000 variant of the IP block,
the DMA reset never succeeds when a MII PHY is used (no problem with a
GMII PHY). The designware_eth_init() function sets the
DMAMAC_SRST bit in the DMA_BUS_MODE register, and then
polls until this bit clears. When a MII PHY is used, with the current
driver, this bit never clears and the driver therefore doesn't work.

The reason is that the PS bit of the GMAC_CONTROL register should be
correctly configured for the DMA reset to work. When the PS bit is 0,
it tells the MAC we have a GMII PHY, when the PS bit is 1, it tells
the MAC we have a MII PHY.

Doing a DMA reset clears all registers, so the PS bit is cleared as
well. This makes the DMA reset work fine with a GMII PHY. However,
with MII PHY, the PS bit should be set.

We have identified this issue thanks to two SPEAr600 platform:

- One equipped with a GMII PHY, with which the existing driver was
working fine.

- One equipped with a MII PHY, where the current driver fails because
the DMA reset times out.

Note: Taken from https://www.spinics.net/lists/netdev/msg432578.html

Signed-off-by: Quentin Schulz &lt;quentin.schulz@bootlin.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
</author>
<published>2018-05-06T21:58:06Z</published>
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<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR</title>
<updated>2018-04-27T18:54:48Z</updated>
<author>
<name>Tom Rini</name>
</author>
<published>2018-04-18T17:50:47Z</published>
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<id>urn:sha1:d024236e5a31a2b4b82cbcc98b31b8170fc88d28</id>
<content type='text'>
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>NET: designware: fix clock enable</title>
<updated>2018-02-26T21:49:26Z</updated>
<author>
<name>Eugeniy Paltsev</name>
</author>
<published>2018-02-06T14:12:09Z</published>
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<id>urn:sha1:1693a577be14a92e61563bad306aa11a359757f5</id>
<content type='text'>
After commit ba1f966725223 ("net: designware: add clock support")
we got NET broken on axs101 and axs103 platforms.

Some clock don't support gating so their clock drivers don't
implement .enable/.disable callbacks. In such case clk_enable
returns -ENOSYS.
Also some clock drivers implement .enable/.disable callbacks not for all
clock IDs and return -ENOSYS (or -ENOTSUPP) for others.

If we have such clock in 'clocks' list of designware ethernet controller
node we fail to probe designware ethernet.

Fix it.

Signed-off-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>net: designware: Pad small packets</title>
<updated>2018-01-15T18:05:21Z</updated>
<author>
<name>Florian Fainelli</name>
</author>
<published>2017-12-09T22:59:55Z</published>
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<id>urn:sha1:7a9ca9db400fc95463011449cf47012fb2e1db0d</id>
<content type='text'>
Make sure that we pad small packets to a minimum length of 60 bytes
(without FCS). This is necessary to interface with Ethernet switches
that will reject RUNT frames unless padded correctly.

Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
</content>
</entry>
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