<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bcm63xx/u-boot/arch/arm/include/asm, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/'/>
<updated>2019-06-19T07:24:57Z</updated>
<entry>
<title>arm: ls1028a: define the integrated PCI bus (ECAM)</title>
<updated>2019-06-19T07:24:57Z</updated>
<author>
<name>Alex Marginean</name>
</author>
<published>2019-06-07T14:03:07Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=062d8148f8a6ed574a45f8b3096ba0226c4b5fca'/>
<id>urn:sha1:062d8148f8a6ed574a45f8b3096ba0226c4b5fca</id>
<content type='text'>
LS1028A includes an integrated PCI bus with 11 PCI functions residing on
bus 0.  ECAM plus the device register space takes up 256MB of address
space.

Signed-off-by: Alex Marginean &lt;alexm.osslist@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: fsl-lsch3: add clock support for the second eSDHC</title>
<updated>2019-06-19T07:24:56Z</updated>
<author>
<name>Yangbo Lu</name>
</author>
<published>2019-05-23T03:05:45Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=087bfe67ac2555c37b257335424b7c193d7f6afd'/>
<id>urn:sha1:087bfe67ac2555c37b257335424b7c193d7f6afd</id>
<content type='text'>
Layerscape began to use two eSDHC controllers, for example,
LS1028A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.

Signed-off-by: Yangbo Lu &lt;yangbo.lu@nxp.com&gt;
Signed-off-by: Yinbo Zhu &lt;yinbo.zhu@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: ls1028a: Add other serdes protocal support</title>
<updated>2019-06-19T07:24:56Z</updated>
<author>
<name>Xiaowei Bao</name>
</author>
<published>2019-05-21T10:28:31Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=36f50b75238ee5a2589763797bc5b5551e4e8ec2'/>
<id>urn:sha1:36f50b75238ee5a2589763797bc5b5551e4e8ec2</id>
<content type='text'>
Add other serdes protocal support.

Signed-off-by: Xiaowei Bao &lt;xiaowei.bao@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: ls1028a: enable workaround for USB erratum A-008997</title>
<updated>2019-06-19T07:24:56Z</updated>
<author>
<name>Ran Wang</name>
</author>
<published>2019-05-14T09:34:56Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=3458a4198cca572f6c82d38810e4f3c80dc8849d'/>
<id>urn:sha1:3458a4198cca572f6c82d38810e4f3c80dc8849d</id>
<content type='text'>
Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL
registers has been moved to DSCR as compared to other Layerscape SoCs
where it was in SCFG.

Signed-off-by: Ran Wang &lt;ran.wang_1@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-imx-20190612' of git://git.denx.de/u-boot-imx</title>
<updated>2019-06-11T17:41:24Z</updated>
<author>
<name>Tom Rini</name>
</author>
<published>2019-06-11T17:41:24Z</published>
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<id>urn:sha1:529faf80c339b78bd361b59735664f2605322b8e</id>
<content type='text'>
u-boot-imx-20190612
--------------------

- Board fixes:
	- imx6logic
	- wandboard
	- mx6sabre boots again
	- imx8qm_mek
	- pico-* boards
	- Toradex apalis / colibri
	- engicam imx6 (environment)
	- KP MX53
	- opos6ul
- Switch to DM:
	- vining2000
	- dh MX6
	- Toradex colibri i.MX7
	- Novena
- Security : fix CSF size for HAB
- Other:
      - imx: fix building for i.mx8 without spl
      - pcie and switch to DM

      mx6sabreauto: Enable SPL SDP support
</content>
</entry>
<entry>
<title>imx: define ARCH_MXC for i.MX8/8M/7ULP</title>
<updated>2019-06-11T08:43:00Z</updated>
<author>
<name>Peng Fan</name>
</author>
<published>2019-05-09T08:33:55Z</published>
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<id>urn:sha1:16529ff255a37df29133ebffc62e59793cbf6d86</id>
<content type='text'>
Without this definition, fsl_esdhc will access reserved registers
on i.MX chips, so define ARCH_MXC to fix it.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
</content>
</entry>
<entry>
<title>imx: drop imx-regs.h</title>
<updated>2019-06-11T08:43:00Z</updated>
<author>
<name>Peng Fan</name>
</author>
<published>2019-05-09T08:33:52Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=75eba1832103e85c7e79c7f71b4deaaadcd6bcef'/>
<id>urn:sha1:75eba1832103e85c7e79c7f71b4deaaadcd6bcef</id>
<content type='text'>
imx-regs.h under arch-imx has no user, drop it.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
</content>
</entry>
<entry>
<title>pico-imx7d: Correct uart clock root</title>
<updated>2019-06-11T08:42:48Z</updated>
<author>
<name>Jun Nie</name>
</author>
<published>2019-05-08T06:38:31Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=79fcbde8eb57a0dfc9761c4ba167186843d7a707'/>
<id>urn:sha1:79fcbde8eb57a0dfc9761c4ba167186843d7a707</id>
<content type='text'>
Correct uart clock root ID. Incorrect ID may result the
clock is gated because rate value 0 is returned in
imx_get_uartclk()

The ID can be ignored if CONFIG_SKIP_LOWLEVEL_INIT is not enabled
because init_clk_uart() will enable all uart clocks in that case.

Signed-off-by: Jun Nie &lt;jun.nie@linaro.org&gt;
</content>
</entry>
<entry>
<title>mx7ulp: Add common plugin codes for mx7ulp</title>
<updated>2019-06-11T08:42:48Z</updated>
<author>
<name>Ye Li</name>
</author>
<published>2019-05-16T03:18:51Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=15bae9a86d16b1e35a71bb745e5b91d8de0dfd34'/>
<id>urn:sha1:15bae9a86d16b1e35a71bb745e5b91d8de0dfd34</id>
<content type='text'>
Add common plugin codes to call ROM's hwcnfg_setup and generate IVT2
header.

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Implement cboot_get_ethaddr()</title>
<updated>2019-06-05T16:16:34Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2019-04-15T09:32:30Z</published>
<link rel='alternate' type='text/html' href='https://git-03.infra.openwrt.org/project/bcm63xx/u-boot/commit/?id=34e12e03c7f4cbd96e584a590d6e091c48ab8e3d'/>
<id>urn:sha1:34e12e03c7f4cbd96e584a590d6e091c48ab8e3d</id>
<content type='text'>
This function will attempt to look up an Ethernet address in the DTB
that was passed in from cboot. It does so by first trying to locate the
default Ethernet device for the board (identified by the "ethernet"
alias) and if found, reads the "local-mac-address" property. If the
"ethernet" alias does not exist, or if it points to a device tree node
that doesn't exist, or if the device tree node that it points to does
not have a "local-mac-address" property or if the value is invalid, it
will fall back to the legacy mechanism of looking for the MAC address
stored in the "nvidia,ethernet-mac" or "nvidia,ether-mac" properties of
the "/chosen" node.

The MAC address is then written to the default Ethernet device for the
board (again identified by the "ethernet" alias) in U-Boot's control
DTB. This allows the device driver for that device to read the MAC
address from the standard location in device tree.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
</feed>
