bcm63xx/atf/lib/psci/psci_on.c, branch master

Adding new optional PSCI hook pwr_domain_on_finish_late

2019-09-26T03:06:44Z

This PSCI hook is similar to pwr_domain_on_finish but is guaranteed to be invoked with the respective core and cluster are participating in coherency. This will be necessary to safely invoke the new GICv3 API which modifies shared GIC data structures concurrently. Change-Id: I8e54f05c9d4ef5712184c9c18ba45ac97a29eb7a Signed-off-by: Madhukar Pappireddy

Sanitise includes across codebase

2019-01-04T10:43:17Z

Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz

PSCI: Fix MISRA defects in ON/OFF/SUSPEND/SYSTEM_OFF

2018-07-24T08:19:04Z

Fix violations of MISRA C-2012 Rules 8.13, 10.1, 10.3, 17.7 and 20.7. Change-Id: I6f45a1069b742aebf9e1d6a403717b1522083f51 Signed-off-by: Antonio Nino Diaz

PSCI: Replace macros by static inline functions

2018-07-20T12:27:31Z

Fix MISRA C-2012 Directive 4.9 and Rule 21.1 defects. Change-Id: I96c216317d38741ee632d2640cd7b36e6723d5c2 Signed-off-by: Antonio Nino Diaz

PSCI: Publish CPU ON event

2017-10-23T07:15:11Z

This allows other EL3 components to subscribe to CPU on events. Update Firmware Design guide to list psci_cpu_on_finish as an available event. Change-Id: Ida774afe0f9cdce4021933fcc33a9527ba7aaae2 Signed-off-by: Jeenu Viswambharan

Address edge case for stale PSCI CPU data in cache

2017-07-26T10:59:00Z

There is a theoretical edge case during CPU_ON where the cache may contain stale data for the target CPU data - this can occur under the following conditions: - the target CPU is in another cluster from the current - the target CPU was the last CPU to shutdown on its cluster - the cluster was removed from coherency as part of the CPU shutdown In this case the cache maintenace that was performed as part of the target CPUs shutdown was not seen by the current CPU's cluster. And so the cache may contain stale data for the target CPU. This patch adds a cache maintenance operation (flush) for the cache-line containing the target CPU data - this ensures that the target CPU data is read from main memory. Change-Id: If8cfd42639b03174f60669429b7f7a757027d0fb Signed-off-by: David Cunado

Fix order of #includes

2017-07-12T13:45:31Z

This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions in order to retain header groupings, minimise changes to imported headers, and where there are headers within the #if and #ifndef statements. Change-Id: I65085a142ba6a83792b26efb47df1329153f1624 Signed-off-by: Isla Mitchell

Use SPDX license identifiers

2017-05-03T08:39:28Z

To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm

PSCI: Build option to enable D-Caches early in warmboot

2017-04-19T11:07:05Z

This patch introduces a build option to enable D-cache early on the CPU after warm boot. This is applicable for platforms which do not require interconnect programming to enable cache coherency (eg: single cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. Fixes ARM-Software/tf-issues#456 Change-Id: I44c8787d116d7217837ced3bcf0b1d3441c8d80e Signed-off-by: Soby Mathew

PSCI: Optimize call paths if all participants are cache-coherent

2017-03-02T11:00:20Z

The current PSCI implementation can apply certain optimizations upon the assumption that all PSCI participants are cache-coherent. - Skip performing cache maintenance during power-up. - Skip performing cache maintenance during power-down: At present, on the power-down path, CPU driver disables caches and MMU, and performs cache maintenance in preparation for powering down the CPU. This means that PSCI must perform additional cache maintenance on the extant stack for correct functioning. If all participating CPUs are cache-coherent, CPU driver would neither disable MMU nor perform cache maintenance. The CPU being powered down, therefore, remain cache-coherent throughout all PSCI call paths. This in turn means that PSCI cache maintenance operations are not required during power down. - Choose spin locks instead of bakery locks: The current PSCI implementation must synchronize both cache-coherent and non-cache-coherent participants. Mutual exclusion primitives are not guaranteed to function on non-coherent memory. For this reason, the current PSCI implementation had to resort to bakery locks. If all participants are cache-coherent, the implementation can enable MMU and data caches early, and substitute bakery locks for spin locks. Spin locks make use of architectural mutual exclusion primitives, and are lighter and faster. The optimizations are applied when HW_ASSISTED_COHERENCY build option is enabled, as it's expected that all PSCI participants are cache-coherent in those systems. Change-Id: Iac51c3ed318ea7e2120f6b6a46fd2db2eae46ede Signed-off-by: Jeenu Viswambharan