bcm63xx/atf/lib/el3_runtime, branch master

Merge "AArch32: Disable Secure Cycle Counter" into integration

2019-09-27T10:55:15Z

AArch32: Disable Secure Cycle Counter

2019-09-26T15:36:02Z

This patch changes implementation for disabling Secure Cycle Counter. For ARMv8.5 the counter gets disabled by setting SDCR.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR.DP bit. In 'include\aarch32\arch.h' header file new ARMv8.5-PMU related definitions were added. Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8 Signed-off-by: Alexei Fedorov

Fix MTE support from causing unused variable warnings

2019-09-20T08:17:55Z

assert() calls are removed in release builds, and if that assert call is the only use of a variable, an unused variable warning will be triggered in a release build. This patch fixes this problem when CTX_INCLUDE_MTE_REGS by not using an intermediate variable to store the results of get_armv8_5_mte_support(). Change-Id: I529e10ec0b2c8650d2c3ab52c4f0cecc0b3a670e Signed-off-by: Justin Chadwell

Merge changes from topic "db/unsigned_long" into integration

2019-09-18T14:30:09Z

* changes: Unsigned long should not be used as per coding guidelines SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64

SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64

2019-09-13T20:51:02Z

AArch64 System register SCTLR_EL1[31:0] is architecturally mapped to AArch32 System register SCTLR[31:0] AArch64 System register ACTLR_EL1[31:0] is architecturally mapped to AArch32 System register ACTLR[31:0]. `u_register_t` should be used when it's important to store the contents of a register in its native size Signed-off-by: Deepika Bhavnani Change-Id: I0055422f8cc0454405e011f53c1c4ddcaceb5779

Refactor ARMv8.3 Pointer Authentication support code

2019-09-13T13:11:59Z

This patch provides the following features and makes modifications listed below: - Individual APIAKey key generation for each CPU. - New key generation on every BL31 warm boot and TSP CPU On event. - Per-CPU storage of APIAKey added in percpu_data[] of cpu_data structure. - `plat_init_apiakey()` function replaced with `plat_init_apkey()` which returns 128-bit value and uses Generic timer physical counter value to increase the randomness of the generated key. The new function can be used for generation of all ARMv8.3-PAuth keys - ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`. - New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively; pauth_disable_el1()` and `pauth_disable_el3()` functions disable PAuth for EL1 and EL3 respectively; `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from cpu-data structure. - Combined `save_gp_pauth_registers()` function replaces calls to `save_gp_registers()` and `pauth_context_save()`; `restore_gp_pauth_registers()` replaces `pauth_context_restore()` and `restore_gp_registers()` calls. - `restore_gp_registers_eret()` function removed with corresponding code placed in `el3_exit()`. - Fixed the issue when `pauth_t pauth_ctx` structure allocated space for 12 uint64_t PAuth registers instead of 10 by removal of macro CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h` and assigning its value to CTX_PAUTH_REGS_END. - Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions in `msr spsel` instruction instead of hard-coded values. - Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI. Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211 Signed-off-by: Alexei Fedorov

Enable MTE support in both secure and non-secure worlds

2019-09-09T15:23:33Z

This patch adds support for the new Memory Tagging Extension arriving in ARMv8.5. MTE support is now enabled by default on systems that support at EL0. To enable it at ELx for both the non-secure and the secure world, the compiler flag CTX_INCLUDE_MTE_REGS includes register saving and restoring when necessary in order to prevent register leakage between the worlds. Change-Id: I2d4ea993d6b11654ea0d4757d00ca20d23acf36c Signed-off-by: Justin Chadwell

AArch64: Disable Secure Cycle Counter

2019-08-21T14:43:24Z

This patch fixes an issue when secure world timing information can be leaked because Secure Cycle Counter is not disabled. For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR_EL0.DP bit. 'include\aarch64\arch.h' header file was tided up and new ARMv8.5-PMU related definitions were added. Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa Signed-off-by: Alexei Fedorov

Enable MTE support unilaterally for Normal World

2019-07-12T08:27:25Z

This patch enables MTE for Normal world if the CPU suppors it. Enabling MTE for secure world will be done later. Change-Id: I9ef64460beaba15e9a9c20ab02da4fb2208b6f7d Signed-off-by: Soby Mathew

Fix restoring APIBKey registers

2019-03-14T12:57:16Z

Instruction key A was incorrectly restored in the instruction key B registers. Change-Id: I4cb81ac72180442c077898509cb696c9d992eda3 Signed-off-by: Sandrine Bailleux