bcm63xx/atf/lib/cpus/aarch32, branch masterBroadcom-s Trusted Firmware Ahttps://git-03.infra.openwrt.org/project/bcm63xx/atf/atom?h=master2019-04-12T10:10:32ZCortex A9:errata 794073 workaround2019-04-12T10:10:32ZJoel Hutton2019-04-10T11:52:52Zurn:sha1:dd4cf2c74566c18adbb04944e6bf7a974276ec16
On Cortex A9 an errata can cause the processor to violate the rules for
speculative fetches when the MMU is off but branch prediction has not
been disabled. The workaround for this is to execute an Invalidate
Entire Branch Prediction Array (BPIALL) followed by a DSB.
see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf
for more details.
Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93
Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
Cortex-A17: Implement workaround for errata 8524232019-03-13T15:40:45ZAmbroise Vincent2019-03-04T13:20:56Zurn:sha1:be10dcde5226ab28ae4bc71f74b26bbbb030cb4b
Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Cortex-A17: Implement workaround for errata 8524212019-03-13T15:40:45ZAmbroise Vincent2019-02-28T16:23:53Zurn:sha1:0b64c194853d631909317c041d5501ec53c3bfef
Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Cortex-A15: Implement workaround for errata 8276712019-03-13T14:05:47ZAmbroise Vincent2019-03-05T09:54:21Zurn:sha1:5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23
This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html
Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Cortex-A15: Implement workaround for errata 8164702019-03-13T14:05:47ZAmbroise Vincent2019-03-04T16:56:26Zurn:sha1:75a1ada95efa78e4133bdd947c64944005a8e5c2
Change-Id: I9755252725be25bfd0147839d7df56888424ff84
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Fixup register handling in aarch32 reset_handler2019-03-08T15:35:30ZHeiko Stuebner2019-03-05T23:29:13Zurn:sha1:c6c10b02b8eec52c8da2f65164c6a0d3c100016b
The BL handover interface stores the bootloader arguments in
registers r9-r12, so when the reset_handler stores the lr pointer
in r10 it clobers one of the arguments.
Adapt to use r8 and adapt the comment about registers allowed
to clober.
I've checked aarch32 reset_handlers and none seem to use higher
registers as far as I can tell.
Fixes: a6f340fe58b9 ("Introduce the new BL handover interface")
Cc: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Merge pull request #1751 from vwadekar/tegra-scatter-file-support2019-03-01T11:23:58ZAntonio Niño Díaz2019-03-01T11:23:58Zurn:sha1:a4acc7f16500d7856f3317f8412665249da7e947
Tegra scatter file supportCortex-A53: Workarounds for 819472, 824069 and 8273192019-02-28T09:56:58ZAmbroise Vincent2019-02-21T14:16:24Zurn:sha1:bd393704d2b12b1abe37eb2b462f5c8418ed0edd
The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.
Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Cortex-A57: Implement workaround for erratum 8171692019-02-28T09:56:58ZAmbroise Vincent2019-02-21T16:35:49Zurn:sha1:5bd2c24f17fa24e8ee9e468c1401c809a97aae53
Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Cortex-A57: Implement workaround for erratum 8146702019-02-28T09:56:58ZAmbroise Vincent2019-02-21T16:35:07Zurn:sha1:0f6fbbd2e512d45eda760b8d6829cd24b94fe6db
Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>