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<title>bcm63xx/atf/include/plat, branch master</title>
<subtitle>Broadcom-s Trusted Firmware A</subtitle>
<id>https://git-03.infra.openwrt.org/project/bcm63xx/atf/atom?h=master</id>
<link rel='self' href='https://git-03.infra.openwrt.org/project/bcm63xx/atf/atom?h=master'/>
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<updated>2019-09-26T03:06:49Z</updated>
<entry>
<title>Migrate ARM platforms to use the new GICv3 API</title>
<updated>2019-09-26T03:06:49Z</updated>
<author>
<name>Madhukar Pappireddy</name>
</author>
<published>2019-06-10T21:54:36Z</published>
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<id>urn:sha1:6806cd2381901d424b40ba3f17d23f5ffa4ca57e</id>
<content type='text'>
This patch invokes the new function gicv3_rdistif_probe() in the
ARM platform specific gicv3 driver. Since this API modifies the
shared GIC related data structure, it must be invoked coherently
by using the platform specific pwr_domain_on_finish_late hook.

Change-Id: I6efb17d5da61545a1c5a6641b8f58472b31e62a8
Signed-off-by: Madhukar Pappireddy &lt;madhukar.pappireddy@arm.com&gt;
</content>
</entry>
<entry>
<title>Refactor ARMv8.3 Pointer Authentication support code</title>
<updated>2019-09-13T13:11:59Z</updated>
<author>
<name>Alexei Fedorov</name>
</author>
<published>2019-09-13T13:11:59Z</published>
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<id>urn:sha1:ed108b56051de5da8024568a06781ce287e86c78</id>
<content type='text'>
This patch provides the following features and makes modifications
listed below:
- Individual APIAKey key generation for each CPU.
- New key generation on every BL31 warm boot and TSP CPU On event.
- Per-CPU storage of APIAKey added in percpu_data[]
  of cpu_data structure.
- `plat_init_apiakey()` function replaced with `plat_init_apkey()`
  which returns 128-bit value and uses Generic timer physical counter
  value to increase the randomness of the generated key.
  The new function can be used for generation of all ARMv8.3-PAuth keys
- ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`.
- New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions
  generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively;
  pauth_disable_el1()` and `pauth_disable_el3()` functions disable
  PAuth for EL1 and EL3 respectively;
  `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from
  cpu-data structure.
- Combined `save_gp_pauth_registers()` function replaces calls to
  `save_gp_registers()` and `pauth_context_save()`;
  `restore_gp_pauth_registers()` replaces `pauth_context_restore()`
  and `restore_gp_registers()` calls.
- `restore_gp_registers_eret()` function removed with corresponding
  code placed in `el3_exit()`.
- Fixed the issue when `pauth_t pauth_ctx` structure allocated space
  for 12 uint64_t PAuth registers instead of 10 by removal of macro
  CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h`
  and assigning its value to CTX_PAUTH_REGS_END.
- Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions
  in `msr	spsel`  instruction instead of hard-coded values.
- Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI.

Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211
Signed-off-by: Alexei Fedorov &lt;Alexei.Fedorov@arm.com&gt;
</content>
</entry>
<entry>
<title>AArch64: Align crash reporting output</title>
<updated>2019-08-15T14:23:27Z</updated>
<author>
<name>Alexei Fedorov</name>
</author>
<published>2019-07-29T12:34:07Z</published>
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<id>urn:sha1:6c6a470fc1c2e1a516214f1f6dbe00ef045d1d0f</id>
<content type='text'>
This patch modifies crash reporting for AArch64 to provide
aligned output of register dump and GIC registers.

Change-Id: I8743bf1d2d6d56086e735df43785ef28051c5fc3
Signed-off-by: Alexei Fedorov &lt;Alexei.Fedorov@arm.com&gt;
</content>
</entry>
<entry>
<title>Switch AARCH32/AARCH64 to __aarch64__</title>
<updated>2019-08-01T20:45:03Z</updated>
<author>
<name>Julius Werner</name>
</author>
<published>2019-07-09T21:02:43Z</published>
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<id>urn:sha1:402b3cf8766fe2cb4ae462f7ee7761d08a1ba56c</id>
<content type='text'>
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner &lt;jwerner@chromium.org&gt;
</content>
</entry>
<entry>
<title>Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__</title>
<updated>2019-08-01T20:14:12Z</updated>
<author>
<name>Julius Werner</name>
</author>
<published>2019-07-09T20:49:11Z</published>
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<id>urn:sha1:d5dfdeb65ff5b7f24dded201d2945c7b74565ce8</id>
<content type='text'>
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.

All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.

Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner &lt;jwerner@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge changes from topic "advk-serror" into integration</title>
<updated>2019-07-26T09:26:14Z</updated>
<author>
<name>Soby Mathew</name>
</author>
<published>2019-07-26T09:26:14Z</published>
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<id>urn:sha1:4129340717c215f3cc3841e32ed0b6cd5baf7ffb</id>
<content type='text'>
* changes:
  marvell/a3700: Prevent SError accessing PCIe link while it is down
  marvell: Switch to xlat_tables_v2
</content>
</entry>
<entry>
<title>arm: Shorten the Firmware Update (FWU) process</title>
<updated>2019-07-23T09:41:41Z</updated>
<author>
<name>Ambroise Vincent</name>
</author>
<published>2019-07-04T13:58:45Z</published>
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<id>urn:sha1:37b70031e027c76fdebe3c2d2edb2da173bcf150</id>
<content type='text'>
The watchdog is configured with a default value of 256 seconds in order
to implement the Trusted Board Boot Requirements.

For the FVP and Juno platforms, the FWU process relies on a watchdog
reset. In order to automate the test of FWU, the length of this process
needs to be as short as possible. Instead of waiting for those 4 minutes
to have a reset by the watchdog, tell it to reset immediately.

There are no side effects as the value of the watchdog's load register
resets to 0xFFFFFFFF.

Tested on Juno.

Change-Id: Ib1aea80ceddc18ff1e0813a5b98dd141ba8a3ff2
Signed-off-by: Ambroise Vincent &lt;ambroise.vincent@arm.com&gt;
</content>
</entry>
<entry>
<title>marvell: Switch to xlat_tables_v2</title>
<updated>2019-07-16T15:04:00Z</updated>
<author>
<name>Remi Pommarel</name>
</author>
<published>2019-07-14T18:34:28Z</published>
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<id>urn:sha1:6e9e15b0b2aa22fca3354417a685320811e243e3</id>
<content type='text'>
Use v2 xlat tables library instead of v1 for marvell platforms.

Signed-off-by: Remi Pommarel &lt;repk@triplefau.lt&gt;
Change-Id: I838a6a878a8353e84eea9529721761b478943f0a
</content>
</entry>
<entry>
<title>n1sdp: add code for DDR ECC enablement and BL33 copy to DDR</title>
<updated>2019-06-26T13:07:51Z</updated>
<author>
<name>Manoj Kumar</name>
</author>
<published>2019-06-21T16:07:13Z</published>
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<id>urn:sha1:de8bc83ee9401acdab20fd8ae1f9cb9bf7ef7829</id>
<content type='text'>
N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
enabling the ECC bits in DMC620. Zeroing out several gigabytes of
memory from SCP is quite time consuming so functions are added that
zeros out the DDR memory from application processor which is
much faster compared to SCP. BL33 binary cannot be copied to DDR memory
before enabling ECC so this is also done by TF-A from IOFPGA-DDR3
memory to main DDR4 memory after ECC is enabled.

Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which
the entire DDR space cannot be accessed as DRAM2 starts in base
0x8080000000. So these macros are redefined for all ARM platforms.

Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846
Signed-off-by: Manoj Kumar &lt;manoj.kumar3@arm.com&gt;
</content>
</entry>
<entry>
<title>Add option for defining platform DRAM2 base</title>
<updated>2019-05-15T10:42:39Z</updated>
<author>
<name>Sami Mujawar</name>
</author>
<published>2019-05-09T12:35:02Z</published>
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<id>urn:sha1:6bb6015f915dbc6a1208358024387a76530d45da</id>
<content type='text'>
The default DRAM2 base address for Arm platforms
is 0x880000000. However, on some platforms the
firmware may want to move the start address to
a different value.

To support this introduce PLAT_ARM_DRAM2_BASE that
defaults to 0x880000000; but can be overridden by
a platform (e.g. in platform_def.h).

Change-Id: I0d81195e06070bc98f376444b48ada2db1666e28
Signed-off-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
</content>
</entry>
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