bcm63xx/atf/include/lib/cpus, branch masterBroadcom-s Trusted Firmware Ahttps://git-03.infra.openwrt.org/project/bcm63xx/atf/atom?h=master2021-12-24T12:15:12ZAdd Broadcom's code for bcm63xx support2021-12-24T12:15:12ZRafał Miłecki2021-12-24T12:15:12Zurn:sha1:e6d46baf3fae79f693f90bf34f7284c3dfc64aef
This includes all bcm63xx families (some of them don't follow that
naming schema - like BCM4908). All that code has been extracted from the
RAXE500_RAXE450-V1.0.8.70_GPL_release.zip .
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__2019-10-11T12:12:24ZBalint Dobszay2019-10-11T12:01:43Zurn:sha1:89632e6aeba8414c1901eecb5d885363c73448f0
Change-Id: I497072575231730a216220f84a6d349a48eaf5e3
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Merge "Neoverse N1 Errata Workaround 1542419" into integration2019-10-07T12:05:26ZSoby Mathew2019-10-07T12:05:26Zurn:sha1:25792ce44332e7d043db2cc2451eb57fb5db7b09Neoverse N1 Errata Workaround 15424192019-10-04T16:31:24Zlaurenw-arm2019-08-20T20:51:24Zurn:sha1:80942622fe760c23f0a677eac48aff37e90f4251
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
Introducing support for Cortex-A65AE2019-10-03T13:38:31ZImre Kis2019-07-22T12:36:30Zurn:sha1:78f02ae2968dd0a78e0e686f8cf0886fa296f4eb
Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422
Signed-off-by: Imre Kis <imre.kis@arm.com>
Introducing support for Cortex-A652019-10-02T16:12:28ZImre Kis2019-07-18T12:30:03Zurn:sha1:6ad216dca5e388f9aa1518a20a81c836c7eb2d21
Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47
Signed-off-by: Imre Kis <imre.kis@arm.com>
Cortex_hercules: Add support for Hercules-AE2019-09-30T11:55:31ZArtsem Artsemenka2019-09-16T14:11:21Zurn:sha1:a4668c36f1fca75bce99cb706ba7c27e0c16454d
Not tested on FVP Model.
Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
mediatek: mt8183: support CPU hotplug2019-09-10T03:25:08Zkenny liang2019-05-02T11:29:25Zurn:sha1:7352f329e8db1ee655ef1a062ef6fc6dabb3bec2
- Add DCM driver
- Add SPMC driver
- Implement core and cluster power on/off handlers
Change-Id: I902002f8ea6f98fd73bf259188162b10d3939c72
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__2019-08-01T20:14:12ZJulius Werner2019-07-09T20:49:11Zurn:sha1:d5dfdeb65ff5b7f24dded201d2945c7b74565ce8
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.
All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.
Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>
Enable AMU for Cortex-Hercules2019-07-31T15:04:03ZBalint Dobszay2019-07-15T09:46:20Zurn:sha1:3d08461a2de15eb9523cb85f11d40457cd109e3f
Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>